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SLA7042M AND SLA7044M
OUTA STROBE A REF/ENABLE A CNTRL SPLY A CLOCK A SERIAL DATA A GROUND A OUT A SENSE A SENSE B OUTB GROUND B STROBE B REF/ENABLE B CNTRL SPLY B CLOCK B SERIAL DATA B OUT B
1
MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVER
The SLA7042M and SLA7044M are designed for high-efficiency and high-performance microstepping operation of 2-phase, unipolar stepper motors. Microstepping provides improved resolution without limiting step rates, and provides much smoother low-speed motor operation. An automated, innovative packaging technology combined with power NMOS FETs and monolithic CMOS logic/control circuitry advances power multi-chip modules (PMCMsTM) toward the complete integration of motion control. Each half of these stepper motor controller/drivers operate independently. The 4-bit shift registers are serially loaded with motor phase information and output current-ratio data (eight levels). The combination of user-selectable current-sensing resistor, linearly adjustable reference voltage, and digitally selected output current ratio provides users with a broad, variable range of of full, half, and microstepping motor control (IOUT [VREF/3 * RS] * Current Ratio). Each PMCM is rated for a maximum motor supply voltage of 46 V and utilizes advanced NMOS FETs for the high-current, high-voltage driver outputs. The avalanche-rated (100 V) FETs provide excellent ON resistance, improved body diodes, and very-fast switching. The multi-chip ratings and performance afford significant benefits and advantages for stepper drives when compared to the higher dissipation and slower switching speeds associated with bipolar transistors. Highly automated manufacturing techniques provide low-cost and exceptionally reliable PMCMs suitable for controlling and directly driving a broad range of 2-phase, unipolar stepper motors. The SLA7042M and SLA7044M are identical except for rDS(on) and output current ratings. Complete applications information is given on the following pages. PWM current is regulated by appropriately choosing current-sensing resistors, a voltage reference, and digitally programmable current ratio. Inputs are compatible with 5 V logic and microprocessors.
SR/LATCH o CONTROL/LOGIC
2 VREF 3 4 5 6 7 8 9 10 11 12 13 VREF VCC 14 15 16 17 18
Dwg. PK-008
Data Sheet 28202A
D/A
ABSOLUTE MAXIMUM RATINGS
at TA = +25C
Load Supply Voltage, VBB . . . . . . . . . . . . 46 V FET Output Voltage, VDS . . . . . . . . . . . 100 V Control Supply Voltage, VDD . . . . . . . . . 7.0 V Peak Output Current, IOUTM (tw 10 s) . . . . . . . . . . . . . . . . 5.0 A Continuous Output Current, IOUT SLA7042M . . . . . . . . . . . . . . . . . . . . . 1.5 A SLA7044M . . . . . . . . . . . . . . . . . . . . . 3.0 A Input Voltage Range, VIN . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Reference Voltage, VREF . . . . . . . . . . . . VDD Package Power Dissipation, PD . See Graph Junction Temperature, TJ . . . . . . . . . +150C Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . -40C to +150C
+
+
VCC
CONTROL/LOGIC
SR/LATCH
D/A
o
BENEFITS AND FEATURES
s s s s s s s s s Cost-Effective, Multi-Chip Solution `Turn-Key' Motion-Control Module Motor Operation to 3 A and 46 V 3rd Generation High-Voltage FETs 100 V, Avalanche-Rated NMOS Low rDS(on) NMOS Outputs Advanced, Improved Body Diodes Microstepping Unipolar Drive High-Efficiency, High-Speed PWM s Independent PWM Current Control (2-Phase) s Digitally Programmable PWM Current Control s Low Component-Count PWM Drive s Low Internal-Power Dissipation s Electrically Isolated Power Tab s Logic IC- and P-Compatible Inputs s Machine-Insertable Package
Always order by complete part number: SLA7042M .
TM
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
FUNCTIONAL BLOCK DIAGRAM
CONTROL SUPPLY 4 15 V REF/ENABLE 3 14 + V DD -1
PROGRAMMABLE PWM OFF TIMER NOISE FILTER
OUT A/B 1 11
OUT 8 18
A/B
DD
ENABLE
V
D/A REF
+
STROBE
2
13
LATCHES PHASE
DATA
6
17
SHIFT REG
CLOCK
5
16 12 7 GROUND CHANNEL A PIN NUMBERS CHANNEL B PIN NUMBERS
Dwg. FK-006
10 9 SENSE
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
Note that channels A and B are electrically isolated.
25
20
R JM = 5.0C/W
15
ALLOWABLE PACKAGE POWER DISSIPATION
10
5
R JA = 28C/W
0 25 50 75 100 TEMPERATURE in C 125 150
Dwg. GK-018-1
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1995, 2004 Allegro MicroSystems, Inc.
TM
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
DC ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V unless otherwise noted.
Limits Characteristic FET Leakage Current FET ON Voltage Symbol IDSS VDS(ON) rDS(on) VSD VDD IDD VIN(1) VIN(0) Logic Input Current IIN(1) IIN(0) REF/ENABLE Input Voltage VREF/EN VIN(1) = VDD VIN(0) = 0 DATA, CLOCK, STROBE, and OUT Enabled DATA, CLOCK, STROBE, and OUT Disabled REF/ENABLE Input Current Step Reference Current Ratio IREF/EN SRCR 0 V VREF/EN 5 V DATA Input = 000X DATA Input = 001X DATA Input = 010X DATA Input = 011X First Bit Entered (X) = Phase Second Bit Entered = LSB Last Bit Entered = MSB DATA Input = 100X DATA Input = 101X DATA Input = 110X DATA Input = 111X
NOTE: Negative current is defined as coming out of (sourcing) the specified device pin.
Test Conditions VDS = 100 V SLA7042M, IOUT = 1.2 A SLA7044M, IOUT = 3 A SLA7042M, IOUT = 1.2 A SLA7044M, IOUT = 3 A SLA7042M, IOUT = -1.2 A SLA7044M, IOUT = -3 A Operating Each controller, VDD = 5.5 V
Min -- -- -- -- -- -- -- 4.5 -- 3.5 -- -- -- 0.4 VDD - 1 -- -- -- -- -- -- -- -- --
Typ -- -- -- -- -- -- -- 5.0 -- -- -- -- -- -- -- -- 0 20 40 55.5 71.4 83 91 100
Max 4.0 800 855 0.67 0.285 1.2 1.6 5.5 7.0 -- 1.5 1.0 -1.0 2.5 -- 1.0 -- -- -- -- -- -- -- --
Units mA mV mV V V V mA V V A A V V A % % % % % % % %
FET ON Resistance
Body Diode Forward Voltage
Control Supply Voltage Control Supply Current Logic Input Voltage
TYPICAL AC CHARACTERISTICS at TA = +25C, VDD = 5 V, IOUT = 1 A, Logic Levels are VDD and Ground
PWM OFF Time DATA Input = 001X ................................................................. 7 s DATA Input = 010X ................................................................. 7 s DATA Input = 011X ................................................................. 9 s DATA Input = 100X ................................................................. 9 s DATA Input = 101X ................................................................. 9 s DATA Input = 110X ................................................................ 11 s Output RiseTime tr DATA Input = 101X ................................................................ 11 s 10% to 90% ........................................................................... 0.5 s 90% to 10% ........................................................................... 0.1 s 50% to 50% ........................................................................... 0.7 s
Output Fall Time tf Strobe-to-Output Switching Time tpd
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
D D
CLOCK
A
B
E
A DATA C C
B
STROBE
F
Dwg. WK-002
SERIAL PORT TIMING CONDITIONS
(TA = +25C, Logic Levels are VDD and Ground)
A. B. C. D. E. F. Minimum Data Active Time Before Clock Falling Edge (Data Set-Up Time) ........... Minimum Data Active Time After Clock Falling Edge (Data Hold Time) .................. Minimum Data Pulse Width ...................................................................................... Minimum Clock Pulse Width .................................................................................... Minimum Time Between Clock and Strobe Falling Edges ....................................... Minimum Strobe Pulse Width ................................................................................... 150 ns 150 ns 350 ns 350 ns 650 ns 500 ns
APPLICATIONS INFORMATION
The SLA7042M and SLA7044M modules integrate two CMOS controller ICs and four NMOS FETs. Each half of the device operates independently, although the CLOCK inputs may be connected together and the STROBE inputs may be connected together. Pulling VREF/EN low (<2.5 V) allows the 4bit shift registers to be serially loaded with motor phase and output currrent ratioing data. The first bit selects the motor phase (logic high = Output A or B, logic low = Output A or B); the next three bits determine the motor current ratio (eight steps, 0% to 100%). The internal D/A converter, in conjunction with a current-sensing resistor and input reference voltage, completes the microstepping current control. Pulling VREF/EN high (within 1 V of VDD) resets the shift register and latches to turn the MOS drivers OFF and inhibits the serial DATA input.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
TM
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
REGULATING THE PWM OUTPUT CURRENT
The output current (and motor coil current) waveform is illustrated in Figure 1. Setting the maximum PWM current trip point to meet the specified full-step running current for the motor, IOUT max (DATA input = 111X = 100% ratio), requires only a current-sensing resistor, RS, and an input reference voltage, VREF/EN, between 0.4 V and 2.5 V. IOUT max VREF/EN 3 * RS
I OUT PHASE A
SERIAL DATA INPUT ENABLE
In a minimum-component application, a voltage divider provides VREF/EN and an npn transistor provides the required pull-down to enable the serial data input as shown in Figure 2. IOUT max R2 R1 + R2 * Vb 3 * RS
P STEPPER MOTOR CONTROL
Alternative REFERENCE/ENABLE input configurations provide for more complete motor control. A tri-state logic element and a voltage divider allows a fixed reference voltage, with both output disable and data enable functions. Complete P control is usually accomplished with a D/A converter as shown in Figure 3. Here, digital control provides an output disable (>VDD - 1 V), VREF, and VEN (<2.5 V).
0
PHASE A
Dwg. WK-001
FIGURE 1. PHASE A COIL CURRENT WAVEFORM
SERIAL DATA
VDD
V BB B
Vb TO CHANNEL B B
R1
O VREF/EN ENABLE DATA PWM OFF-TIME CONTROL
A
A
D/A
CONTROL LOGIC DRIVE
R2
SENSE
RS
Dwg. EK-011
FIGURE 2. PWM CONTROL (RUN MODE)
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
Vb R1 V DD TO OTHER CHANNEL (OPTIONAL)
D/A R2 H = OFF Z = REFERENCE L = ENABLE DATA
V
REF/EN
......
FROM P 111...1 = OFF 000...0 = ENABLE DATA
Dwg. EK-012
FIGURE 3. COMPLETE CONTROL
SERIAL DATA INPUT
The serial DATA input port is enabled (active low) by the REFERENCE/ENABLE input. When VREF/EN is between 0.4 V and 2.5 V, information on the DATA input is read into the shift register on each high-to-low transition of the CLOCK. There are four bits: the first bit entered controls the
motor phase -- a high level enables OUTA or OUTB, a low level enables OUTA or OUTB. The next three bits set the step reference voltage ratio and PWM OFF time as shown in the Characteristics Tables -- the least-significant bit first and the most-significant bit last. Data written into the serial data port is latched and becomes active on a high-to-low transition at STROBE.
LOAD CURRENT
(NOT TO SCALE) DISABLED
0
VDD VDD - 1 V
MOTOR PWM OPERATION
2.5 V REFERENCE/ENABLE 0
ENTER DATA
3.1 s
MIN
VDD CLOCK 0
VDD SERIAL DATA 0
DON'T CARE
0
100 = 20%
0
DATA LATCHED
010 = 40%
VDD STROBE 0
Dwg. WK-003A
FIGURE 4. TIMING RELATIONSHIPS
TM
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
REFERENCE/ENABLE INPUT
The serial DATA input port is enabled (active low) by the REFERENCE/ENABLE input when VREF/EN is between 0.4 V and 2.5 V. With VREF/EN greater than VDD - 1 V, the serial DATA input port is disabled, the outputs are OFF, and the controller/driver will not be affected by changes at the DATA, CLOCK, or STROBE inputs. With VREF/EN between 0.4 V and 2.5 V, the output current limit is a linear function of VREF and the step reference current ratio. VREF IOUT * SRCR 3 * RS In a typical (SLA7042M) application where VDD = 5 V, a VREF/EN between 0.4 V and 2.5 V, and a maximum allowable load current of 1.2 A, the maximum value of RS is 0.69 and IOUTmin is 0.11 A when SRCR is 100% (DATA input = 111X).
TEMPERATURE EFFECTS ON FET rDS(on)
Analyzing safe, reliable operation includes a concern for the relationship of NMOS ON resistance to junction temperature. Device package power calculations must include the increase in ON resistance (producing higher output ON voltages) caused by higher operating junction temperatures. Figure 5 provides a normalized ON resistance curve, and all thermal calculations should consider increases from the given +25C limits, which may be caused by internal heating during normal operation.
2.5
NORMALIZED FET ON RESISTANCE
2.0
1.5
POWER DISSIPATION CALCULATIONS
The SLA7042/44M normally do not require special heat sinking except under unusual circumstances (two phases operating near maximum output current and TA >65C). However, as with all power drivers, the basic constituents of power dissipation should be evaluated. Conduction losses (internal power dissipation) include: (a) FET output power dissipation (IOUT2 * rDS(on) or IOUT * VDS(ON)), (b) FET body diode power dissipation (VSD * IOUT), and (c) control circuit power dissipation (VDD * IDD).
1.0
0.5
0 -40 0 +40 +80 JUNCTION TEMPERATURE in C +120 +160
Dwg. GK-017
FIGURE 5. NORMALIZED ON RESISTANCE vs TEMPERATURE The power MOSFET outputs of these devices are similar to the International Rectifier type IRL510 (SLA7042M) and IRL520 (SLA7044M). These devices feature an excellent combination of fast switching, ruggedized device design, low on-resistance, and cost effectiveness.
PACKAGE RATINGS/DERATING FACTORS
Thermal calculations must also consider the temperature effects on the output FET ON resistance. The applicable thermal ratings for the 18-lead power-tab SIP PMCM package are: RJA = 28C/W (junction to ambient with no heat sink) or 4.5 W at +25C and a derating factor of -36 mW/C for operation above +25C. RJM = 5C/W (junction to mounting surface).
SLA7042M AND SLA7044M MICROSTEPPING, UNIPOLAR PWM, HIGH-CURRENT MOTOR CONTROLLER/DRIVERS
Dimensions in Inches (for reference only)
1.22 0.008 0.126
0.006
0.126 0.006 x 0.150 0.189
0.008
o
0.961 0.008 0.646
0.008
0.067
0.004
0.008
0.630
0.008
0.390
0.008
0.512
0.096
0.008
0.264
0.020
0.118 1 1.232 0.008 0.026 -0.004
+0.008
18
0.022 +0.008 -0.004 0.066
0.016
0.157
0.028
Dwg MK-002-18 in
Dimensions in Millimeters (controlling dimensions)
310.2 3.2
0.15
3.2 0.15 x 3.8 4.8
0.2
o
24.4 0.2 16.4 0.2
1.7
0.1
16 0.2
9.9 0.2
13 0.2
2.45
0.2
6.7
0.5
3.0 1 31.3 0.2 0.65 -0.1
+0.2
18 1.68
0.4
0.55 +0.2 -0.1 4.0
0.7
Dwg. MK-002-18 mm
The products described here are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc. Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of their products. The information included herein is believed to be accurate and reliable. However, Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. assume no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Recommended mounting hardware torque: 4.34 - 5.79 lbf*ft (6 - 8 kgf*cm or 0.588 - 0.784 Nm). 3. The shaded area is exposed (electrically isolated) heat spreader. 4. Recommend use of metal-oxide-filled, alkyl-degenerated oil base, silicone grease (Dow Corning 340 or equivalent). TM
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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